M29F800DB70N6T TR

M29F800DT M29F800DB 8 Mbit (1Mb x8 or 512Kb x16, Boot Block) 5V Supply Flash Memory Feature summary ■ Supply voltage – VCC = 5V ±10% for Program, Erase and Read ■ Access time: 55, 70, 90ns ■ Programming time – 10µs per Byte/Word typical ■ 19 Memory Blocks – 1 Boot Block (Top or Bottom location) – 2 Parameter and 16 Main Blocks ■ Program/Erase controller – Embedded Byte/Word Program algorithms ■ Erase Suspend and Resume modes – Read and Program another Block during Erase Suspend ■ Unlock Bypass Program command – Faster Production/batch Programming ■ Temporary Block Unprotection mode ■ Common Flash Interface – 64 bit Security Code ■ Low power consumption – Standby and Automatic Standby ■ 100,000 Program/Erase cycles per Block ■ Electronic Signature – Manufacturer Code: 0020h – Top Device Code M29F800DT: 22ECh – Bottom Device Code M29F800DB: 2258h August 2006 SO44 (M) TSOP48 (N) 12 x 20mm Rev 5 1/53 www.st.com 1 Contents M29F800DT Contents 1 Summary description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2 Signal descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 3 4 2/53 2.0.1 Address Inputs (A0-A18) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0.2 Data Inputs/Outputs (DQ0-DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0.3 Data Inputs/Outputs (DQ8-DQ14) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0.4 Data Input/Output or Address Input (DQ15A-1) . . . . . . . . . . . . . . . . . . . 12 2.0.5 Chip Enable (E) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0.6 Output Enable (G) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0.7 Write Enable (W) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 2.0.8 Reset/Block Temporary Unprotect (RP) . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.0.9 Ready/Busy output (RB) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.0.10 Byte/Word Organization Select (BYTE) . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.0.11 VCC Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 2.0.12 VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0.1 Bus Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0.2 Bus Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0.3 Output Disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0.4 Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0.5 Automatic Standby . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 3.0.6 Special bus operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0.7 Electronic Signature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 3.0.8 Block Protection and Blocks Unprotection . . . . . . . . . . . . . . . . . . . . . . . 15 Command Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.1 Read/Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.2 Auto Select command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 4.0.3 Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.4 Unlock Bypass command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.5 Unlock Bypass Program command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.6 Unlock Bypass Reset command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 4.0.7 Chip Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 4.0.8 Block Erase command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 M29F800DT 5 Contents 4.0.9 Erase Suspend command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0.10 Erase Resume command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0.11 Read CFI Query command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 4.0.12 Block Protect and Chip Unprotect commands . . . . . . . . . . . . . . . . . . . . 19 Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0.1 Data Polling Bit (DQ7) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0.2 Toggle Bit (DQ6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 5.0.3 Error Bit (DQ5) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0.4 Erase Timer Bit (DQ3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 5.0.5 Alternative Toggle Bit (DQ2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 6 Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 7 DC and AC parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 8 Package mechanical . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 9 Part numbering . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Appendix A Block address table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Appendix B Common Flash Interface (CFI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Appendix C Block protection. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.1 Programmer technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 9.2 In-System technique . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 3/53 List of tables M29F800DT List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Table 18. Table 19. Table 20. Table 21. Table 22. Table 23. Table 24. Table 25. Table 26. Table 27. Table 28. 4/53 Signal names . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Bus operations, BYTE = VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Bus operations, BYTE = VIH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Commands, 16-bit mode, BYTE = VIH . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Commands, 8-bit mode, BYTE = VIL. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Program, Erase times and Program, Erase Endurance cycles. . . . . . . . . . . . . . . . . . . . . . 21 Status Register Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Operating and AC measurement conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Device capacitance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 DC characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Read AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Write AC characteristics, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Write AC characteristics, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Reset/Block Temporary Unprotect AC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 SO44 – 44 lead Plastic Small Outline, 525 mils body width, package mechanical data. . . 36 TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data . . . 37 Ordering information scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Top Boot Block addresses, M29F800D . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Bottom Boot Block addresses, M29F800DB . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Query structure overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 CFI Query Identification String . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 CFI Query System Interface Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 Device Geometry Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Primary Algorithm-specific Extended Query table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Security Code Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Programmer technique bus operations, BYTE = VIH or VIL . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 M29F800DT List of figures List of figures Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Logic diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 SO connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 TSOP connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block addresses (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Block addresses (x16) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Data Polling flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Data Toggle flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 AC measurement I/O waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 AC measurement Load Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Read Mode AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Write AC waveforms, Write Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Write AC waveforms, Chip Enable controlled . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Reset/Block Temporary Unprotect AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 SO44 - 44 lead Plastic Small Outline, 525 mils body width, package outline . . . . . . . . . . . 36 TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline . . . . . . . . . . . 37 Programmer Equipment Block Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 Programmer Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 In-System Equipment Block Protect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 In-System Equipment Chip Unprotect flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 5/53 Summary description 1 M29F800DT Summary description The M29F800D is a 8 Mbit (1Mb x8 or 512Kb x16) non-volatile memory that can be read, erased and reprogrammed. These operations can be performed using a single low voltage (5V) supply. On power-up the memory defaults to its Read mode where it can be read in the same way as a ROM or EPROM. The memory is divided into blocks that can be erased independently so it is possible to preserve valid data while old data is erased. Each block can be protected independently to prevent accidental Program or Erase commands from modifying the memory. Program and Erase commands are written to the Command Interface of the memory. An on-chip Program/Erase Controller simplifies the process of programming or erasing the memory by taking care of all of the special operations that are required to update the memory contents. The end of a program or erase operation can be detected and any error conditions identified. The command set required to control the memory is consistent with JEDEC standards. The blocks in the memory are asymmetrically arranged, see Figure 4: Block addresses (x8), and Figure 5: Block addresses (x16). The first or last 64 Kbytes have been divided into four additional blocks. The 16 Kbyte Boot Block can be used for small initialization code to start the microprocessor, the two 8 Kbyte Parameter Blocks can be used for parameter storage and the remaining 32K is a small Main Block where the application may be stored. Chip Enable, Output Enable and Write Enable signals control the bus operation of the memory. They allow simple connection to most microprocessors, often without additional logic. The memory is offered in SO44 and TSOP48 (12 x 20mm) packages. The memory is supplied with all the bits erased (set to ’1’). 6/53 M29F800DT Summary description Figure 1. Logic diagram VCC 19 15 A0-A18 DQ0-DQ14 DQ15A–1 W E M29F800DT M29F800DB G RB RP BYTE VSS AI06148B Table 1. Signal names A0-A18 Address Inputs DQ0-DQ7 Data Inputs/Outputs DQ8-DQ14 Data Inputs/Outputs DQ15A–1 Data Input/Output or address Input E Chip Enable G Output Enable W Write Enable RP Reset/Block Temporary Unprotect RB Ready/Busy Output BYTE Byte/Word Organization Select VCC Supply voltage VSS Ground NC Not Connected Internally 7/53 Summary description Figure 2. M29F800DT SO connections RB A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 E VSS G DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 44 2 43 3 42 4 41 5 40 6 39 7 38 8 37 9 36 10 35 11 M29F800DT 34 12 M29F800DB 33 13 32 14 31 15 30 16 29 28 17 27 18 26 19 25 20 21 24 22 23 RP W A8 A9 A10 A11 A12 A13 A14 A15 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC AI06150 8/53 M29F800DT Summary description Figure 3. TSOP connections A15 A14 A13 A12 A11 A10 A9 A8 NC NC W RP NC NC RB A18 A17 A7 A6 A5 A4 A3 A2 A1 1 12 13 24 48 M29F800DT M29F800DB 37 36 25 A16 BYTE VSS DQ15A–1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 G VSS E A0 AI06149 9/53 Summary description Figure 4. M29F800DT Block addresses (x8) M29F800DT Top Boot Block Addresses (x8) M29F800DB Bottom Boot Block Addresses (x8) FFFFFh FFFFFh 16 KByte 64 KByte FC000h FBFFFh F0000h EFFFFh 8 KByte 64 KByte FA000h F9FFFh E0000h Total of 15 64 KByte Blocks 8 KByte F8000h F7FFFh 32 KByte F0000h EFFFFh 1FFFFh 64 KByte 64 KByte E0000h 10000h 0FFFFh 32 KByte Total of 15 64 KByte Blocks 1FFFFh 08000h 07FFFh 8 KByte 06000h 05FFFh 64 KByte 10000h 0FFFFh 8 KByte 04000h 03FFFh 64 KByte 00000h 16 KByte 00000h 1. Also see Appendix A, Table 19, and Table 20 for a full listing of the Block addresses. 10/53 M29F800DT Summary description Figure 5. Block addresses (x16) M29F800DT Top Boot Block Addresses (x16) M29F800DB Bottom Boot Block Addresses (x16) 7FFFFh 7FFFFh 8 KWord 32 KWord 7E000h 7DFFFh 78000h 77FFFh 4 KWord 32 KWord 7D000h 7CFFFh 70000h Total of 15 32 KWord Blocks 4 KWord 7C000h 7BFFFh 16 KWord 78000h 77FFFh 0FFFFh 32 KWord 32 KWord 70000h 08000h 07FFFh 16 KWord Total of 15 32 KWord Blocks 0FFFFh 04000h 03FFFh 4 KWord 03000h 02FFFh 32 KWord 08000h 07FFFh 4 KWord 02000h 01FFFh 32 KWord 00000h 8 KWord 00000h 1. Also see Appendix A, Table 19, and Table 20 for a full listing of the Block addresses. 11/53 Signal descriptions 2 M29F800DT Signal descriptions See Figure 1: Logic diagram, and Table 1: Signal names for a brief overview of the signals connected to this device. 2.0.1 Address Inputs (A0-A18) The Address Inputs select the cells in the memory array to access during Bus Read operations. During Bus Write operations they control the commands sent to the Command Interface of the internal state machine. 2.0.2 Data Inputs/Outputs (DQ0-DQ7) The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation. During Bus Write operations they represent the commands sent to the Command Interface of the internal state machine. 2.0.3 Data Inputs/Outputs (DQ8-DQ14) The Data Inputs/Outputs output the data stored at the selected address during a Bus Read operation when BYTE is High, VIH. When BYTE is Low, VIL, these pins are not used and are high impedance. During Bus Write operations the Command Register does not use these bits. When reading the Status Register these bits should be ignored. 2.0.4 Data Input/Output or Address Input (DQ15A-1) When BYTE is High, VIH, this pin behaves as a Data Input/Output pin (as DQ8-DQ14). When BYTE is Low, VIL, this pin behaves as an address pin; DQ15A–1 Low will select the LSB of the Word on the other addresses, DQ15A–1 High will select the MSB. Throughout the text consider references to the Data Input/Output to include this pin when BYTE is High and references to the Address Inputs to include this pin when BYTE is Low except when stated explicitly otherwise. 2.0.5 Chip Enable (E) The Chip Enable, E, activates the memory, allowing Bus Read and Bus Write operations to be performed. When Chip Enable is High, VIH, all other pins are ignored. 2.0.6 Output Enable (G) The Output Enable, G, controls the Bus Read operation of the memory. 2.0.7 Write Enable (W) The Write Enable, W, controls the Bus Write operation of the memory’s Command Interface. 12/53 M29F800DT 2.0.8 Signal descriptions Reset/Block Temporary Unprotect (RP) The Reset/Block Temporary Unprotect pin can be used to apply a Hardware Reset to the memory or to temporarily unprotect all Blocks that have been protected. A Hardware Reset is achieved by holding Reset/Block Temporary Unprotect Low, VIL, for at least tPLPX. After Reset/Block Temporary Unprotect goes High, VIH, the memory will be ready for Bus Read and Bus Write operations after tPHEL or tRHEL, whichever occurs last. See Section 2.0.9: Ready/Busy output (RB), Table 15: Reset/Block Temporary Unprotect AC characteristics, and Figure 13: Reset/Block Temporary Unprotect AC waveforms for more details. Holding RP at VID will temporarily unprotect the protected Blocks in the memory. Program and Erase operations on all blocks will be possible. The transition from VIH to VID must be slower than tPHPHH. 2.0.9 Ready/Busy output (RB) The Ready/Busy pin is an open-drain output that can be used to identify when the device is performing a Program or Erase operation. During Program or Erase operations Ready/Busy is Low, VOL. Ready/Busy is high-impedance during Read mode, Auto Select mode and Erase Suspend mode. After a Hardware Reset, Bus Read and Bus Write operations cannot begin until Ready/Busy becomes high-impedance. See Table 15: Reset/Block Temporary Unprotect AC characteristics, and Figure 13: Reset/Block Temporary Unprotect AC waveforms. The use of an open-drain output allows the Ready/Busy pins from several memories to be connected to a single pull-up resistor. A Low will then indicate that one, or more, of the memories is busy. 2.0.10 Byte/Word Organization Select (BYTE) The Byte/Word Organization Select pin is used to switch between the 8-bit and 16-bit Bus modes of the memory. When Byte/Word Organization Select is Low, VIL, the memory is in 8bit mode, when it is High, VIH, the memory is in 16-bit mode. 2.0.11 VCC Supply Voltage The VCC Supply Voltage supplies the power for all operations (Read, Program, Erase etc.). The Command Interface is disabled when the VCC Supply Voltage is less than the Lockout voltage, VLKO. This prevents Bus Write operations from accidentally damaging the data during power up, power down and power surges. If the Program/Erase Controller is programming or erasing during this time then the operation aborts and the memory contents being altered will be invalid. A 0.1µF capacitor should be connected between the VCC Supply Voltage pin and the VSS Ground pin to decouple the current surges from the power supply. The PCB track widths must be sufficient to carry the currents required during program and erase operations, ICC3. 2.0.12 VSS Ground The VSS Ground is the reference for all voltage measurements. 13/53 Bus operations 3 M29F800DT Bus operations There are five standard bus operations that control the device. These are Bus Read, Bus Write, Output Disable, Standby and Automatic Standby. See Table 2: Bus operations, BYTE = VIL, and Table 3: Bus operations, BYTE = VIH for a summary. Typically glitches of less than 5ns on Chip Enable or Write Enable are ignored by the memory and do not affect bus operations. 3.0.1 Bus Read Bus Read operations read from the memory cells, or specific registers in the Command Interface. A valid Bus Read operation involves setting the desired address on the Address Inputs, applying a Low signal, VIL, to Chip Enable and Output Enable and keeping Write Enable High, VIH. The Data Inputs/Outputs will output the value, see Figure 10: Read Mode AC waveforms, and Table 12: Read AC characteristics for details of when the output becomes valid. 3.0.2 Bus Write Bus Write operations write to the Command Interface. A valid Bus Write operation begins by setting the desired address on the Address Inputs. The Address Inputs are latched by the Command Interface on the falling edge of Chip Enable or Write Enable, whichever occurs last. The Data Inputs/Outputs are latched by the Command Interface on the rising edge of Chip Enable or Write Enable, whichever occurs first. Output Enable must remain High, VIH, during the whole Bus Write operation. See Figure 11: Write AC waveforms, Write Enable controlled, Figure 12: Write AC waveforms, Chip Enable controlled, Table 13: Write AC characteristics, Write Enable controlled, and Table 14: Write AC characteristics, Chip Enable controlled, for details of the timing requirements. 3.0.3 Output Disable The Data Inputs/Outputs are in the high impedance state when Output Enable is High, VIH. 3.0.4 Standby When Chip Enable is High, VIH, the memory enters Standby mode and the Data Inputs/Outputs pins are placed in the high-impedance state. To reduce the Supply Current to the Standby Supply Current, ICC2, Chip Enable should be held within VCC ± 0.2V. For the Standby current level see Table 11: DC characteristics. During program or erase operations the memory will continue to use the Program/Erase Supply Current, ICC3, for Program or Erase operations until the operation completes. 3.0.5 Automatic Standby If CMOS levels (VCC ± 0.2V) are used to drive the bus and the bus is inactive for 150ns or more the memory enters Automatic Standby where the internal Supply Current is reduced to the Standby Supply Current, ICC2. The Data Inputs/Outputs will still output data if a Bus Read operation is in progress. 14/53 M29F800DT 3.0.6 Bus operations Special bus operations Additional bus operations can be performed to read the Electronic Signature and also to apply and remove Block Protection. These bus operations are intended for use by programming equipment and are not usually used in applications. They require VID to be applied to some pins. 3.0.7 Electronic Signature The memory has two codes, the manufacturer code and the device code, that can be read to identify the memory. These codes can be read by applying the signals listed in Table 2: Bus operations, BYTE = VIL, and Table 3: Bus operations, BYTE = VIH. 3.0.8 Block Protection and Blocks Unprotection Each block can be separately protected against accidental Program or Erase. Protected blocks can be unprotected to allow data to be changed. There are two methods available for protecting and unprotecting the blocks, one for use on programming equipment and the other for in-system use. Block Protect and Chip Unprotect operations are described in Appendix C. Bus operations, BYTE = VIL(1) Table 2. Operation E G Address Inputs DQ15A–1, A0-A18 W Data Inputs/Outputs DQ14-DQ8 DQ7-DQ0 Bus Read VIL VIL VIH Cell address Hi-Z Data Output Bus Write VIL VIH VIL Command address Hi-Z Data Input X VIH VIH X Hi-Z Hi-Z Standby VIH X X X Hi-Z Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z 20h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH Hi-Z ECh (M29F800DT) 58h (M29F800DB) Output Disable 1. X = VIL or VIH. Bus operations, BYTE = VIH(1) Table 3. Operation Address Inputs A0-A18 Data Inputs/Outputs DQ15A–1, DQ14-DQ0 E G W Bus Read VIL VIL VIH Cell address Bus Write VIL VIH VIL Command address X VIH VIH X Hi-Z Standby VIH X X X Hi-Z Read Manufacturer Code VIL VIL VIH A0 = VIL, A1 = VIL, A9 = VID, Others VIL or VIH 0020h Read Device Code VIL VIL VIH A0 = VIH, A1 = VIL, A9 = VID, Others VIL or VIH 22ECh (M29F800DT) 2258h (M29F800DB) Output Disable Data Output Data Input 1. X = VIL or VIH. 15/53 Command Interface 4 M29F800DT Command Interface All Bus Write operations to the memory are interpreted by the Command Interface. Commands consist of one or more sequential Bus Write operations. Failure to observe a valid sequence of Bus Write operations will result in the memory returning to Read mode. The long command sequences are imposed to maximize data security. The address used for the commands changes depending on whether the memory is in 16bit or 8-bit mode. See either Table 4, or Table 5, depending on the configuration that is being used, for a summary of the commands. 4.0.1 Read/Reset command The Read/Reset command returns the memory to its Read mode where it behaves like a ROM or EPROM, unless otherwise stated. It also resets the errors in the Status Register. Either one or three Bus Write operations can be used to issue the Read/Reset command. The Read/Reset Command can be issued, between Bus Write cycles before the start of a program or erase operation, to return the device to read mode. Once the program or erase operation has started the Read/Reset command is no longer accepted. The Read/Reset command will not abort an Erase operation when issued while in Erase Suspend. 4.0.2 Auto Select command The Auto Select command is used to read the Manufacturer Code, the Device Code and the Block Protection Status. Three consecutive Bus Write operations are required to issue the Auto Select command. Once the Auto Select command is issued the memory remains in Auto Select mode until a Read/Reset command is issued. Read CFI Query and Read/Reset commands are accepted in Auto Select mode, all other commands are ignored. From the Auto Select mode the Manufacturer Code can be read using a Bus Read operation with A0 = VIL and A1 = VIL. The other address bits may be set to either VIL or VIH. The Manufacturer Code for STMicroelectronics is 0020h. The Device Code can be read using a Bus Read operation with A0 = VIH and A1 = VIL. The other address bits may be set to either VIL or VIH. The Block Protection Status of each block can be read using a Bus Read operation with A0 = VIL, A1 = VIH, and A12-A18 specifying the address of the block. The other address bits may be set to either VIL or VIH. If the addressed block is protected then 01h is output on Data Inputs/Outputs DQ0-DQ7, otherwise 00h is output. 16/53 M29F800DT 4.0.3 Command Interface Program command The Program command can be used to program a value to one address in the memory array at a time. The command requires four Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. If the address falls in a protected block then the Program command is ignored, the data remains unchanged. The Status Register is never read and no error condition is given. During the program operation the memory will ignore all commands. It is not possible to issue any command to abort or pause the operation. Typical program times are given in Table 6: Program, Erase times and Program, Erase Endurance cycles. Bus Read operations during the program operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status Register, for more details. After the program operation has completed the memory will return to the Read mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. Note that the Program command cannot change a bit set at ’0’ back to ’1’. One of the Erase Commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’. 4.0.4 Unlock Bypass command The Unlock Bypass command is used in conjunction with the Unlock Bypass Program command to program the memory. When the access time to the device is long (as with some EPROM programmers) considerable time saving can be made by using these commands. Three Bus Write operations are required to issue the Unlock Bypass command. Once the Unlock Bypass command has been issued the memory will only accept the Unlock Bypass Program command and the Unlock Bypass Reset command. The memory can be read as if in Read mode. 4.0.5 Unlock Bypass Program command The Unlock Bypass Program command can be used to program one address in memory at a time. The command requires two Bus Write operations, the final write operation latches the address and data in the internal state machine and starts the Program/Erase Controller. The Program operation using the Unlock Bypass Program command behaves identically to the Program operation using the Program command. A protected block cannot be programmed; the operation cannot be aborted and the Status Register is read. Errors must be reset using the Read/Reset command, which leaves the device in Unlock Bypass Mode. See the Program command for details on the behavior. 4.0.6 Unlock Bypass Reset command The Unlock Bypass Reset command can be used to return to Read/Reset mode from Unlock Bypass Mode. Two Bus Write operations are required to issue the Unlock Bypass Reset command. Read/Reset command does not exit from Unlock Bypass Mode. 17/53 Command Interface 4.0.7 M29F800DT Chip Erase command The Chip Erase command can be used to erase the entire chip. Six Bus Write operations are required to issue the Chip Erase Command and start the Program/Erase Controller. If any blocks are protected then these are ignored and all the other blocks are erased. If all of the blocks are protected the Chip Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the erase operation the memory will ignore all commands. It is not possible to issue any command to abort the operation. Typical chip erase times are given in Table 6. All Bus Read operations during the Chip Erase operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status Register, for more details. After the Chip Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read Mode. The Chip Erase Command sets all of the bits in unprotected blocks of the memory to ’1’. All previous data is lost. 4.0.8 Block Erase command The Block Erase command can be used to erase a list of one or more blocks. Six Bus Write operations are required to select the first block in the list. Each additional block in the list can be selected by repeating the sixth Bus Write operation using the address of the additional block. The Block Erase operation starts the Program/Erase Controller about 50µs after the last Bus Write operation. Once the Program/Erase Controller starts it is not possible to select any more blocks. Each additional block must therefore be selected within 50µs of the last block. The 50µs timer restarts when an additional block is selected. The Status Register can be read after the sixth Bus Write operation. See the Status Register for details on how to identify if the Program/Erase Controller has started the Block Erase operation. If any selected blocks are protected then these are ignored and all the other selected blocks are erased. If all of the selected blocks are protected the Block Erase operation appears to start but will terminate within about 100µs, leaving the data unchanged. No error condition is given when protected blocks are ignored. During the Block Erase operation the memory will ignore all commands except the Erase Suspend command. Typical block erase times are given in Table 6. All Bus Read operations during the Block Erase operation will output the Status Register on the Data Inputs/Outputs. See Section 5: Status Register, for more details. After the Block Erase operation has completed the memory will return to the Read Mode, unless an error has occurred. When an error occurs the memory will continue to output the Status Register. A Read/Reset command must be issued to reset the error condition and return to Read mode. The Block Erase Command sets all of the bits in the unprotected selected blocks to ’1’. All previous data in the selected blocks is lost. 18/53 M29F800DT 4.0.9 Command Interface Erase Suspend command The Erase Suspend command may be used to temporarily suspend a Block Erase operation and return the memory to Read mode. The command requires one Bus Write operation. The Program/Erase Controller will suspend within the Erase Suspend Latency Time (refer to Table 6 for value) of the Erase Suspend command being issued. Once the Program/Erase Controller has stopped the memory will be set to Read mode and the Erase will be suspended. If the Erase Suspend command is issued during the period when the memory is waiting for an additional block (before the Program/Erase Controller starts) then the Erase is suspended immediately and will start immediately when the Erase Resume command is issued. It is not possible to select any further blocks to erase after the Erase Resume. During Erase Suspend it is possible to Read and Program cells in blocks that are not being erased; both Read and Program operations behave as normal on these blocks. If any attempt is made to program in a protected block or in the suspended block then the Program command is ignored and the data remains unchanged. The Status Register is not read and no error condition is given. Reading from blocks that are being erased will output the Status Register. It is also possible to issue the Auto Select, Read CFI Query and Unlock Bypass commands during an Erase Suspend. The Read/Reset command must be issued to return the device to Read Array mode before the Resume command will be accepted. 4.0.10 Erase Resume command The Erase Resume command must be used to restart the Program/Erase Controller from Erase Suspend. An erase can be suspended and resumed more than once. 4.0.11 Read CFI Query command The Read CFI Query Command is used to read data from the Common Flash Interface (CFI) Memory Area. This command is valid when the device is ready to read the array data or when the device is in autoselected mode. One Bus Write cycle is required to issue the Read CFI Query Command. Once the command is issued subsequent Bus Read operations read from the Common Flash Interface Memory Area. The Read/Reset command must be issued to return the device to Read Array mode. See Appendix B, Table 21, Table 22, Table 23, Table 24, Table 25, and Appendix B: Common Flash Interface (CFI), for details on the information contained in the Common Flash Interface (CFI) memory area. 4.0.12 Block Protect and Chip Unprotect commands Each block can be separately protected against accidental Program or Erase. The whole chip can be unprotected to allow the data inside the blocks to be changed. Block Protect and Chip Unprotect operations are described in Appendix C. 19/53 Command Interface Table 4. M29F800DT Commands, 16-bit mode, BYTE = VIH(1) Command Length Bus Write operations 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X F0 3 555 AA 2AA 55 X F0 Auto Select 3 555 AA 2AA 55 555 90 Program 4 555 AA 2AA 55 555 A0 Unlock Bypass 3 555 AA 2AA 55 555 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 555 AA 2AA 55 555 Block Erase 6+ 555 AA 2AA 55 555 Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 55 98 Read/Reset PA PD 80 555 AA 2AA 55 555 10 80 555 AA 2AA 55 BA 30 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. 20/53 M29F800DT Table 5. Command Interface Commands, 8-bit mode, BYTE = VIL(1) Command Length Bus Write operations 1st 2nd 3rd 4th 5th 6th Addr Data Addr Data Addr Data Addr Data Addr Data Addr Data 1 X F0 3 AAA AA 555 55 X F0 Auto Select 3 AAA AA 555 55 AAA 90 Program 4 AAA AA 555 55 AAA A0 Unlock Bypass 3 AAA AA 555 55 AAA 20 Unlock Bypass Program 2 X A0 PA PD Unlock Bypass Reset 2 X 90 X 00 Chip Erase 6 AAA AA 555 55 AAA Block Erase 6+ AAA AA 555 55 AAA Erase Suspend 1 X B0 Erase Resume 1 X 30 Read CFI Query 1 AA 98 Read/Reset PA PD 80 AAA AA 555 55 AAA 10 80 AAA AA 555 55 BA 30 1. X Don’t Care, PA Program Address, PD Program Data, BA Any address in the Block. All values in the table are in hexadecimal. The Command Interface only uses A–1, A0-A10 and DQ0-DQ7 to verify the commands; A11-A18, DQ8DQ14 and DQ15 are Don’t Care. DQ15A–1 is A–1 when BYTE is VIL or DQ15 when BYTE is VIH. Table 6. Program, Erase times and Program, Erase Endurance cycles Parameter Min Chip Erase Typ(1)(2) Max(2) Unit 12 60(3) s Block Erase (64 Kbytes) 0.8 Erase Suspend Latency time 30 (4) 6 s µs Program (Byte or Word) 10 200(3) Chip Program (Byte by Byte) 12 60(3) s 6 30(3) s Chip Program (Word by Word) Program/Erase cycles (per Block) Data Retention µs 100,000 cycles 20 years 1. Typical values measured at room temperature and nominal voltages. 2. Sampled, but not 100% tested. 3. Maximum value measured at worst case conditions for both temperature and VCC after 100,00 program/erase cycles. 4. Maximum value measured at worst case conditions for both temperature and VCC. 21/53 Status Register 5 M29F800DT Status Register Bus Read operations from any address always read the Status Register during Program and Erase operations. It is also read during Erase Suspend when an address within a block being erased is accessed. The bits in the Status Register are summarized in Table 7: Status Register Bits. 5.0.1 Data Polling Bit (DQ7) The Data Polling Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Data Polling Bit is output on DQ7 when the Status Register is read. During Program operations the Data Polling Bit outputs the complement of the bit being programmed to DQ7. After successful completion of the Program operation the memory returns to Read mode and Bus Read operations from the address just programmed output DQ7, not its complement. During Erase operations the Data Polling Bit outputs ’0’, the complement of the erased state of DQ7. After successful completion of the Erase operation the memory returns to Read Mode. In Erase Suspend mode the Data Polling Bit will output a ’1’ during a Bus Read operation within a block being erased. The Data Polling Bit will change from a ’0’ to a ’1’ when the Program/Erase Controller has suspended the Erase operation. Figure 6: Data Polling flowchart, gives an example of how to use the Data Polling Bit. A Valid Address is the address being programmed or an address within the block being erased. 5.0.2 Toggle Bit (DQ6) The Toggle Bit can be used to identify whether the Program/Erase Controller has successfully completed its operation or if it has responded to an Erase Suspend. The Toggle Bit is output on DQ6 when the Status Register is read. During Program and Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations at any address. After successful completion of the operation the memory returns to Read mode. During Erase Suspend mode the Toggle Bit will output when addressing a cell within a block being erased. The Toggle Bit will stop toggling when the Program/Erase Controller has suspended the Erase operation. If any attempt is made to erase a protected block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 100µs. If any attempt is made to program a protected block or a suspended block, the operation is aborted, no error is signalled and DQ6 toggles for approximately 1µs. Figure 7: Data Toggle flowchart, gives an example of how to use the Data Toggle Bit. 22/53 M29F800DT 5.0.3 Status Register Error Bit (DQ5) The Error Bit can be used to identify errors detected by the Program/Erase Controller. The Error Bit is set to ’1’ when a Program, Block Erase or Chip Erase operation fails to write the correct data to the memory. If the Error Bit is set a Read/Reset command must be issued before other commands are issued. The Error bit is output on DQ5 when the Status Register is read. Note that the Program command cannot change a bit set to ’0’ back to ’1’ and attempting to do so will set DQ5 to ‘1’. A Bus Read operation to that address will show the bit is still ‘0’. One of the Erase commands must be used to set all the bits in a block or in the whole memory from ’0’ to ’1’ 5.0.4 Erase Timer Bit (DQ3) The Erase Timer Bit can be used to identify the start of Program/Erase Controller operation during a Block Erase command. Once the Program/Erase Controller starts erasing the Erase Timer Bit is set to ’1’. Before the Program/Erase Controller starts the Erase Timer Bit is set to ’0’ and additional blocks to be erased may be written to the Command Interface. The Erase Timer Bit is output on DQ3 when the Status Register is read. 5.0.5 Alternative Toggle Bit (DQ2) The Alternative Toggle Bit can be used to monitor the Program/Erase controller during Erase operations. The Alternative Toggle Bit is output on DQ2 when the Status Register is read. During Chip Erase and Block Erase operations the Toggle Bit changes from ’0’ to ’1’ to ’0’, etc., with successive Bus Read operations from addresses within the blocks being erased. A protected block is treated the same as a block not being erased. Once the operation completes the memory returns to Read mode. During Erase Suspend the Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read operations from addresses within the blocks being erased. Bus Read operations to addresses within blocks not being erased will output the memory cell data as if in Read mode. After an Erase operation that causes the Error Bit to be set the Alternative Toggle Bit can be used to identify which block or blocks have caused the error. The Alternative Toggle Bit changes from ’0’ to ’1’ to ’0’, etc. with successive Bus Read Operations from addresses within blocks that have not erased correctly. The Alternative Toggle Bit does not change if the addressed block has erased correctly. 23/53 Status Register M29F800DT Table 7. Status Register Bits(1) Operation Address DQ7 DQ6 DQ5 DQ3 DQ2 RB Program Any address DQ7 Toggle 0 – – 0 Program during Erase Suspend Any address DQ7 Toggle 0 – – 0 Program Error Any address DQ7 Toggle 1 – – 0 Chip Erase Any address 0 Toggle 0 1 Toggle 0 Block Erase before timeout Erasing Block 0 Toggle 0 0 Toggle 0 Non-Erasing Block 0 Toggle 0 0 No Toggle 0 Erasing Block 0 Toggle 0 1 Toggle 0 Non-Erasing Block 0 Toggle 0 1 No Toggle 0 Erasing Block 1 No Toggle 0 – Toggle 1 Block Erase Erase Suspend Non-Erasing Block Data read as normal 1 Good Block address 0 Toggle 1 1 No Toggle 0 Faulty Block address 0 Toggle 1 1 Toggle 0 Erase Error 1. Unspecified data bits should be ignored. Figure 6. Data Polling flowchart START READ DQ5 & DQ7 at VALID ADDRESS DQ7 = DATA YES NO NO DQ5 =1 YES READ DQ7 at VALID ADDRESS DQ7 = DATA YES NO FAIL PASS AI03598 24/53 M29F800DT Status Register Figure 7. Data Toggle flowchart START READ DQ6 READ DQ5 & DQ6 DQ6 = TOGGLE NO YES NO DQ5 =1 YES READ DQ6 TWICE DQ6 = TOGGLE NO YES FAIL PASS AI01370C 25/53 Maximum rating 6 M29F800DT Maximum rating Stressing the device above the rating listed in the Absolute Maximum Ratings" table may cause permanent damage to the device. Exposure to Absolute Maximum Rating conditions for extended periods may affect device reliability. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Refer also to the STMicroelectronics SURE Program and other relevant quality documents. Table 8. Absolute maximum ratings Symbol Parameter Min Max Unit TBIAS Temperature under bias –50 125 °C TSTG Storage temperature –65 150 °C –0.6 VCC +0.6 V voltage(1)(2) VIO Input or Output VCC Supply voltage –0.6 6 V VID Identification voltage –0.6 13.5 V 1. Minimum voltage may undershoot to –2V during transition and for less than 20ns during transitions. 2. Maximum voltage may overshoot to VCC +2V during transition and for less than 20ns during transitions. 26/53 M29F800DT 7 DC and AC parameters DC and AC parameters This section summarizes the operating measurement conditions, and the DC and AC characteristics of the device. The parameters in the DC and AC characteristics Tables that follow, are derived from tests performed under the Measurement Conditions summarized in Table 9: Operating and AC measurement conditions. Designers should check that the operating conditions in their circuit match the operating conditions when relying on the quoted parameters. Table 9. Operating and AC measurement conditions M29F800D 55 Parameter 70/ 90 Unit Min Max Min Max 4.5 5.5 4.5 5.5 V Ambient Operating Temperature (range 1) 0 70 0 70 °C Ambient Operating Temperature (range 6) –40 85 –40 85 °C VCC Supply voltage Load capacitance (CL) 30 Input Rise and Fall times 10 Input Pulse voltages Input and Output Timing Ref. voltages Figure 8. 100 pF 10 ns 0 to 3 0.45 to 2.4 V 1.5 0.8 and 2.0 V AC measurement I/O waveform High Speed (55ns) 3V 1.5V 0V Standard (70, 90ns) 2.4V 0.45V 2.0V 0.8V AI05276 27/53 DC and AC parameters Figure 9. M29F800DT AC measurement Load Circuit 1.3V VCC 1N914 3.3kΩ DEVICE UNDER TEST OUT CL 0.1µF CL includes JIG capacitance Table 10. Symbol CIN COUT Device capacitance(1) Parameter Input capacitance Output capacitance 1. Sampled only, not 100% tested. 28/53 AI05277 Test Condition Min Max Unit VIN = 0V 6 pF VOUT = 0V 12 pF M29F800DT Table 11. DC and AC parameters DC characteristics Symbol Parameter Test condition Min Max Unit 0V ≤VIN ≤VCC ±1 µA 0V ≤VOUT ≤VCC ±1 µA E = VIL, G = VIH, f = 6MHz 20 mA E = VIH 2 mA ILI Input Leakage Current ILO Output Leakage Current ICC1 Supply Current (Read) ICC2 Supply Current (Standby) TTL ICC3 Supply Current (Standby) CMOS E = VCC ±0.2V, RP = VCC ±0.2V 150 µA Supply Current (Program/Erase) Program/Erase Controller active 20 mA ICC4 (1) VIL Input Low voltage –0.5 0.8 V VIH Input High voltage 2 VCC + 0.5 V VOL Output Low voltage 0.45 V VOH Output High voltage TTL CMOS VID Identification voltage IID Identification Current VLKO IOL = 5.8mA IOH = –2.5mA 2.4 11.5 A9 = VID Program/Erase Lockout Supply voltage 3.2 V 12.5 V 100 µA 4.2 V 1. Sampled only, not 100% tested. Figure 10. Read Mode AC waveforms tAVAV A0-A18/ A–1 VALID tAVQV tAXQX E tELQV tEHQX tELQX tEHQZ G tGLQX tGHQX tGLQV tGHQZ DQ0-DQ7/ DQ8-DQ15 VALID tBHQV BYTE tELBL/tELBH tBLQZ AI06154 29/53 DC and AC parameters Table 12. M29F800DT Read AC characteristics M29F800D Symbol Alt Parameter Test condition Unit 55 70/ 90 tAVAV tRC Address Valid to Next Address Valid E = VIL, G = VIL Min 55 70 ns tAVQV tACC Address Valid to Output Valid E = VIL, G = VIL Max 55 70 ns tELQX(1) tLZ Chip Enable Low to Output Transition G = VIL Min 0 0 ns tELQV tCE Chip Enable Low to Output Valid G = VIL Max 55 70 ns tGLQX(1) tOLZ Output Enable Low to Output Transition E = VIL Min 0 0 ns tGLQV tOE Output Enable Low to Output Valid E = VIL Max 30 30 ns tEHQZ(1) tHZ Chip Enable High to Output Hi-Z G = VIL Max 18 20 ns tGHQZ(1) tDF Output Enable High to Output Hi-Z E = VIL Max 18 20 ns tEHQX tGHQX tAXQX tOH Chip Enable, Output Enable or Address Transition to Output Transition Min 0 0 ns tELBL tELBH tELFL tELFH Chip Enable to BYTE Low or High Max 5 5 ns tBLQZ tFLQZ BYTE Low to Output Hi-Z Max 25 30 ns tBHQV tFHQV BYTE High to Output Valid Max 30 40 ns 1. Sampled only, not 100% tested. 30/53 M29F800DT DC and AC parameters Figure 11. Write AC waveforms, Write Enable controlled tAVAV A0-A18/ A–1 VALID tWLAX tAVWL tWHEH E tELWL tWHGL G tGHWL tWLWH W tWHWL tDVWH DQ0-DQ7/ DQ8-DQ15 tWHDX VALID VCC tVCHEL RB tWHRL AI06155 31/53 DC and AC parameters Table 13. M29F800DT Write AC characteristics, Write Enable controlled M29F800D Symbol Alt Parameter Unit 55 70/ 90 tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns tELWL tCS Chip Enable Low to Write Enable Low Min 0 0 ns tWLWH tWP Write Enable Low to Write Enable High Min 45 45 ns tDVWH tDS Input Valid to Write Enable High Min 45 45 ns tWHDX tDH Write Enable High to Input Transition Min 0 0 ns tWHEH tCH Write Enable High to Chip Enable High Min 0 0 ns tWHWL tWPH Write Enable High to Write Enable Low Min 20 20 ns tAVWL tAS Address Valid to Write Enable Low Min 0 0 ns tWLAX tAH Write Enable Low to Address Transition Min 45 45 ns Output Enable High to Write Enable Low Min 0 0 ns tOEH Write Enable High to Output Enable Low Min 0 0 ns tBUSY Program/Erase Valid to RB Low Max 30 30 ns tVCS VCC High to Chip Enable Low Min 50 50 µs tGHWL tWHGL tWHRL (1) tVCHEL 1. Sampled only, not 100% tested. Figure 12. Write AC waveforms, Chip Enable controlled tAVAV A0-A18/ A–1 VALID tELAX tAVEL tEHWH W tWLEL tEHGL G tGHEL tELEH E tEHEL tDVEH DQ0-DQ7/ DQ8-DQ15 tEHDX VALID VCC tVCHWL RB tEHRL 32/53 AI06156 M29F800DT DC and AC parameters Table 14. Write AC characteristics, Chip Enable controlled M29F800D Symbol Alt Parameter Unit 55 70/ 90 tAVAV tWC Address Valid to Next Address Valid Min 55 70 ns tWLEL tWS Write Enable Low to Chip Enable Low Min 0 0 ns tELEH tCP Chip Enable Low to Chip Enable High Min 45 45 ns tDVEH tDS Input Valid to Chip Enable High Min 45 45 ns tEHDX tDH Chip Enable High to Input Transition Min 0 0 ns tEHWH tWH Chip Enable High to Write Enable High Min 0 0 ns tEHEL tCPH Chip Enable High to Chip Enable Low Min 20 20 ns tAVEL tAS Address Valid to Chip Enable Low Min 0 0 ns tELAX tAH Chip Enable Low to Address Transition Min 45 45 ns Output Enable High Chip Enable Low Min 0 0 ns tGHEL tEHGL tOEH Chip Enable High to Output Enable Low Min 0 0 ns tEHRL(1) tBUSY Program/Erase Valid to RB Low Max 30 30 ns tVCHWL tVCS VCC High to Write Enable Low Min 50 50 µs 1. Sampled only, not 100% tested. Figure 13. Reset/Block Temporary Unprotect AC waveforms W, E, G tPHWL, tPHEL, tPHGL RB tRHWL, tRHEL, tRHGL RP tPLPX tPHPHH tPLYH AI06870 33/53 DC and AC parameters Table 15. M29F800DT Reset/Block Temporary Unprotect AC characteristics M29F800D Symbol Alt Parameter 70/ 90 tPHWL(1) tPHEL tPHGL(1) tRH RP High to Write Enable Low, Chip Enable Low, Output Enable Low Min 50 50 ns tRHWL(1) tRHEL(1) tRHGL(1) tRB RB High to Write Enable Low, Chip Enable Low, Output Enable Low Min 0 0 ns tPLPX tRP RP Pulse Width Min 500 500 ns tPLYH(1) tREADY RP Low to Read Mode Max 10 10 µs tPHPHH(1) tVIDR RP Rise Time to VID Min 500 500 ns 1. Sampled only, not 100% tested. 34/53 Unit 55 M29F800DT 8 Package mechanical Package mechanical In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 35/53 Package mechanical M29F800DT Figure 14. SO44 - 44 lead Plastic Small Outline, 525 mils body width, package outline A A2 C b e CP D N E EH 1 A1 α L SO-d 1. Drawing is not to scale. Table 16. SO44 – 44 lead Plastic Small Outline, 525 mils body width, package mechanical data millimeters inches Symbol Typ Min A Typ Min 2.80 A1 Max 0.1102 0.10 0.0039 A2 2.30 2.20 2.40 0.0906 0.0866 0.0945 b 0.40 0.35 0.50 0.0157 0.0138 0.0197 C 0.15 0.10 0.20 0.0059 0.0039 0.0079 CP 0.08 0.0030 D 28.20 28.00 28.40 1.1102 1.1024 1.1181 E 13.30 13.20 13.50 0.5236 0.5197 0.5315 EH 16.00 15.75 16.25 0.6299 0.6201 0.6398 e 1.27 – – 0.0500 – – L 0.80 α N 36/53 Max 0.0315 8° 44 8° 44 M29F800DT Package mechanical Figure 15. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline 1 48 e D1 B 24 L1 25 A2 E1 E A A1 DIE α L C CP TSOP-G 1. Drawing is not to scale. Table 17. TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data millimeters inches Symbol Typ Min A Max Typ Min 1.200 Max 0.0472 A1 0.100 0.050 0.150 0.0039 0.0020 0.0059 A2 1.000 0.950 1.050 0.0394 0.0374 0.0413 B 0.220 0.170 0.270 0.0087 0.0067 0.0106 0.100 0.210 0.0039 0.0083 C CP 0.080 0.0031 D1 12.000 11.900 12.100 0.4724 0.4685 0.4764 E 20.000 19.800 20.200 0.7874 0.7795 0.7953 E1 18.400 18.300 18.500 0.7244 0.7205 0.7283 e 0.500 – – 0.0197 – – L 0.600 0.500 0.700 0.0236 0.0197 0.0276 L1 0.800 α 3° 0 5° 0.0315 0 5° 3° 37/53 Part numbering 9 M29F800DT Part numbering Table 18. Ordering information scheme Example: M29 F 800DB Device Type M29 Operating Voltage F = VCC = 5V ± 10% Device Function 800D = 8 Mbit (x8/x16), Boot Block Array Matrix T = Top Boot B = Bottom Boot Speed 55 = 55 ns 70 = 70 ns 90 = 90 ns Package M = SO44 N = TSOP48: 12 x 20 mm Temperature Range 1 = 0 to 70 °C 6 = –40 to 85 °C Option E = ECOPACK® package, standard package F = ECOPACK® package, tape & reel 24mm packing 38/53 55 N 6 T M29F800DT Part numbering Devices are shipped from the factory with the memory content bits erased to ’1’. For a list of available options (Speed, Package, etc.) or for further information on any aspect of this device, please contact the ST Sales Office nearest to you. 39/53 Block address table Appendix A T Table 19. 40/53 M29F800DT Block address table Top Boot Block addresses, M29F800D # Size (Kbytes) Address range (x8) Address range (x16) 18 16 FC000h-FFFFFh 7E000h-7FFFFh 17 8 FA000h-FBFFFh 7D000h-7DFFFh 16 8 F8000h-F9FFFh 7C000h-7CFFFh 15 32 F0000h-F7FFFh 78000h-7BFFFh 14 64 E0000h-EFFFFh 70000h-77FFFh 13 64 D0000h-DFFFFh 68000h-6FFFFh 12 64 C0000h-CFFFFh 60000h-67FFFh 11 64 B0000h-BFFFFh 58000h-5FFFFh 10 64 A0000h-AFFFFh 50000h-57FFFh 9 64 90000h-9FFFFh 48000h-4FFFFh 8 64 80000h-8FFFFh 40000h-47FFFh 7 64 70000h-7FFFFh 38000h-3FFFFh 6 64 60000h-6FFFFh 30000h-37FFFh 5 64 50000h-5FFFFh 28000h-2FFFFh 4 64 40000h-4FFFFh 20000h-27FFFh 3 64 30000h-3FFFFh 18000h-1FFFFh 2 64 20000h-2FFFFh 10000h-17FFFh 1 64 10000h-1FFFFh 08000h-0FFFFh 0 64 00000h-0FFFFh 00000h-07FFFh M29F800DT Block address table Table 20. Bottom Boot Block addresses, M29F800DB # Size (Kbytes) Address range (x8) Address range (x16) 18 64 F0000h-FFFFFh 78000h-7FFFFh 17 64 E0000h-EFFFFh 70000h-77FFFh 16 64 D0000h-DFFFFh 68000h-6FFFFh 15 64 C0000h-CFFFFh 60000h-67FFFh 14 64 B0000h-BFFFFh 58000h-5FFFFh 13 64 A0000h-AFFFFh 50000h-57FFFh 12 64 90000h-9FFFFh 48000h-4FFFFh 11 64 80000h-8FFFFh 40000h-47FFFh 10 64 70000h-7FFFFh 38000h-3FFFFh 9 64 60000h-6FFFFh 30000h-37FFFh 8 64 50000h-5FFFFh 28000h-2FFFFh 7 64 40000h-4FFFFh 20000h-27FFFh 6 64 30000h-3FFFFh 18000h-1FFFFh 5 64 20000h-2FFFFh 10000h-17FFFh 4 64 10000h-1FFFFh 08000h-0FFFFh 3 32 08000h-0FFFFh 04000h-07FFFh 2 8 06000h-07FFFh 03000h-03FFFh 1 8 04000h-05FFFh 02000h-02FFFh 0 16 00000h-03FFFh 00000h-01FFFh 41/53 Common Flash Interface (CFI) Appendix B M29F800DT Common Flash Interface (CFI) The Common Flash Interface is a JEDEC approved, standardized data structure that can be read from the Flash memory device. It allows a system software to query the device to determine various electrical and timing parameters, density information and functions supported by the memory. The system can interface easily with the device, enabling the software to upgrade itself when necessary. When the CFI Query Command is issued the device enters CFI Query mode and the data structure is read from the memory. Table 21, Table 22, Table 23, Table 24, Table 25, and Table 26 show the addresses used to retrieve the data. The CFI data structure also contains a security area where a 64 bit unique security number is written (see Table 26: Security Code Area). This area can be accessed only in Read mode by the final user. It is impossible to change the security number after it has been written by ST. Issue a Read command to return to Read mode. Table 21. Query structure overview(1) Address Sub-section name Description x16 x8 10h 20h CFI Query Identification String Command set ID and algorithm data offset 1Bh 36h System Interface Information Device timing & voltage information 27h 4Eh Device Geometry Definition Flash device layout 40h 80h Primary Algorithm-specific Extended Query table Additional information specific to the Primary Algorithm (optional) 61h C2h Security Code Area 64 bit unique device number 1. Query data are always presented on the lowest order data outputs. 42/53 M29F800DT Common Flash Interface (CFI) CFI Query Identification String(1) Table 22. Address Data x16 x8 10h 20h 0051h 11h 22h 0052h 12h 24h 0059h 13h 26h 0002h 14h 28h 0000h 15h 2Ah 0040h 16h 2Ch 0000h 17h 2Eh 0000h 18h 30h 19h 1Ah Description Value "Q" Query Unique ASCII String "QRY" "R" "Y" Primary Algorithm Command Set and Control Interface ID code 16 bit ID code defining a specific algorithm AMD Compatible Address for Primary Algorithm extended Query table (see Table 24) P = 40h Alternate Vendor Command Set and Control Interface ID Code second vendor - specified algorithm supported NA 0000h 32h 0000h Address for Alternate Algorithm extended Query table 34h 0000h NA 1. Query data are always presented on the lowest order data outputs (DQ7-DQ0) only. DQ8-DQ15 are ‘0’. Table 23. CFI Query System Interface Information Address Data Description Value x16 x8 1Bh 36h VCC Logic Supply Minimum Program/Erase voltage 0045h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 4.5V 1Ch 38h VCC Logic Supply Maximum Program/Erase voltage 0055h bit 7 to 4BCD value in volts bit 3 to 0BCD value in 100 mV 5.5V 1Dh 3Ah 0000h VPP [Programming] Supply Minimum Program/Erase voltage NA 1Eh 3Ch 0000h VPP [Programming] Supply Maximum Program/Erase voltage NA 1Fh 3Eh n 0004h Typical timeout per single byte/word program = 2 µs 20h 40h 0000h Typical timeout for minimum size write buffer program = 21h 42h 000Ah Typical timeout per individual block erase = 2n ms 2n 16µs 2n µs NA 1s see note(1) 22h 44h 0000h Typical timeout for full chip erase = 23h 46h 0004h Maximum timeout for byte/word program = 2n times typical ms n 256µs 24h 48h 0000h Maximum timeout for write buffer program = 2 times typical NA 25h 4Ah 0003h Maximum timeout per individual block erase = 2n times typical 8s 26h 4Ch n 0000h Maximum timeout for chip erase = 2 times typical see note(1) 1. Not supported in the CFI 43/53 Common Flash Interface (CFI) Table 24. M29F800DT Device Geometry Definition Address Data 44/53 Description Value x16 x8 27h 4Eh 0014h Device Size = 2n in number of bytes 1 MByte 28h 29h 50h 52h 0002h 0000h Flash Device Interface Code description x8, x16 Async. 2Ah 2Bh 54h 56h 0000h 0000h Maximum number of bytes in multi-byte program or page = 2n NA 2Ch 58h 0004h Number of Erase Block Regions within the device. It specifies the number of regions within the device containing contiguous Erase Blocks of the same size. 4 2Dh 2Eh 5Ah 5Ch 0000h 0000h Region 1 Information Number of identical size erase block = 0000h+1 1 2Fh 30h 5Eh 60h 0040h 0000h Region 1 Information Block size in Region 1 = 0040h * 256 byte 31h 32h 62h 64h 0001h 0000h Region 2 Information Number of identical size erase block = 0001h+1 33h 34h 66h 68h 0020h 0000h Region 2 Information Block size in Region 2 = 0020h * 256 byte 35h 36h 6Ah 6Ch 0000h 0000h Region 3 Information Number of identical size erase block = 0000h+1 37h 38h 6Eh 70h 0080h 0000h Region 3 Information Block size in Region 3 = 0080h * 256 byte 39h 3Ah 72h 74h 000Eh 0000h Region 4 Information Number of identical-size erase block = 000Eh+1 3Bh 3Ch 76h 78h 0000h 0001h Region 4 Information Block size in Region 4 = 0100h * 256 byte 16 Kbyte 2 8 Kbyte 1 32 Kbyte 15 64 Kbyte M29F800DT Common Flash Interface (CFI) Table 25. Primary Algorithm-specific Extended Query table Address Data Description Value x16 x8 40h 80h 0050h "P" 41h 82h 0052h Primary Algorithm Extended Query table unique ASCII string “PRI” "R" 42h 84h 0049h "I" 43h 86h 0031h Major version number, ASCII "1" 44h 88h 0030h Minor version number, ASCII "0" 45h 8Ah Address Sensitive Unlock (bits 1 to 0) 0000h 00 = required, 01= not required Silicon Revision Number (bits 7 to 2) Yes 46h 8Ch 0002h Erase Suspend 00 = not supported, 01 = Read only, 02 = Read and Write 2 47h 8Eh 0001h Block Protection 00 = not supported, x = number of sectors in per group 1 48h 90h 0001h Temporary Block Unprotect 00 = not supported, 01 = supported 49h 92h 0004h Block Protect /Unprotect 04 = M29W400B 4Ah 94h 0000h Simultaneous Operations, 00 = not supported No 4Bh 96h 0000h Burst Mode, 00 = not supported, 01 = supported No 4Ch 98h 0000h Table 26. Yes 4 Page Mode, 00 = not supported, 01 = 4 page word, 02 = 8 page word No Security Code Area Address Data x16 x8 61h C3h, C2h XXXX 62h C5h, C4h XXXX 63h C7h, C6h XXXX 64h C9h, C8h XXXX Description 64 bit: unique device number 45/53 Block protection Appendix C M29F800DT Block protection Block protection can be used to prevent any operation from modifying the data stored in the Flash. Each Block can be protected individually. Once protected, Program and Erase operations on the block fail to change the data. There are three techniques that can be used to control Block Protection, these are the Programmer technique, the In-System technique and Temporary Unprotection. Temporary Unprotection is controlled by the Reset/Block Temporary Unprotection pin, RP; this is described in the Signal Descriptions section. Unlike the Command Interface of the Program/Erase Controller, the techniques for protecting and unprotecting blocks change between different Flash memory suppliers. For example, the techniques for AMD parts will not work on STMicroelectronics parts. Care should be taken when changing drivers for one part to work on another. 9.1 Programmer technique The Programmer technique uses high (VID) voltage levels on some of the bus pins. These cannot be achieved using a standard microprocessor bus, therefore the technique is recommended only for use in Programming Equipment. To protect a block follow the flowchart in Figure 16: Programmer Equipment Block Protect flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all blocks can be unprotected at the same time. To unprotect the chip follow Figure 17: Programmer Equipment Chip Unprotect flowchart. Table 27: Programmer technique bus operations, BYTE = VIH or VIL, gives a summary of each operation. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 9.2 In-System technique The In-System technique requires a high voltage level on the Reset/Blocks Temporary Unprotect pin, RP. This can be achieved without violating the maximum ratings of the components on the microprocessor bus, therefore this technique is suitable for use after the Flash has been fitted to the system. To protect a block follow the flowchart in Figure 18: In-System Equipment Block Protect flowchart. To unprotect the whole chip it is necessary to protect all of the blocks first, then all the blocks can be unprotected at the same time. To unprotect the chip follow Figure 19: InSystem Equipment Chip Unprotect flowchart. The timing on these flowcharts is critical. Care should be taken to ensure that, where a pause is specified, it is followed as closely as possible. Do not allow the microprocessor to service interrupts that will upset the timing and do not abort the procedure before reaching the end. Chip Unprotect can take several seconds and a user message should be provided to show that the operation is progressing. 46/53 M29F800DT Table 27. Block protection Programmer technique bus operations, BYTE = VIH or VIL E G W Address Inputs A0-A18 Data Inputs/Outputs DQ15A–1, DQ14-DQ0 Block Protect VIL VID VIL Pulse A9 = VID, A12-A18 Block address Others = X X Chip Unprotect VID VID VIL Pulse A9 = VID, A12 = VIH, A15 = VIH Others = X X Block Protection verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIL, A9 = VID, A12-A18 Block address Others = X Pass = XX01h Retry = XX00h Block Unprotection verify VIL VIL VIH A0 = VIL, A1 = VIH, A6 = VIH, A9 = VID, A12-A18 Block address Others = X Retry = XX01h Pass = XX00h Operation 47/53 Block protection M29F800DT Figure 16. Programmer Equipment Block Protect flowchart START Set-up ADDRESS = BLOCK ADDRESS W = VIH n=0 G, A9 = VID, E = VIL Protect Wait 4µs W = VIL Wait 100µs W = VIH E, G = VIH, A0, A6 = VIL, A1 = VIH E = VIL Verify Wait 4µs G = VIL Wait 60ns Read DATA DATA NO = 01h YES A9 = VIH E, G = VIH ++n = 25 NO End YES PASS A9 = VIH E, G = VIH FAIL 48/53 AI03469 M29F800DT Block protection Figure 17. Programmer Equipment Chip Unprotect flowchart START Set-up PROTECT ALL BLOCKS n=0 CURRENT BLOCK = 0 A6, A12, A15 = VIH(1) E, G, A9 = VID Unprotect Wait 4µs W = VIL Wait 10ms W = VIH E, G = VIH ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1, A6 = VIH E = VIL Wait 4µs G = VIL INCREMENT CURRENT BLOCK Verify Wait 60ns Read DATA NO End NO ++n = 1000 DATA = 00h YES LAST BLOCK YES YES A9 = VIH E, G = VIH A9 = VIH E, G = VIH FAIL PASS NO AI03470 49/53 Block protection M29F800DT Figure 18. In-System Equipment Block Protect flowchart Set-up START n=0 RP = VID Protect WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL WRITE 60h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 100µs Verify WRITE 40h ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL Wait 4µs READ DATA ADDRESS = BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIL DATA NO = 01h YES End RP = VIH ISSUE READ/RESET COMMAND PASS ++n = 25 NO YES RP = VIH ISSUE READ/RESET COMMAND FAIL AI03471 50/53 M29F800DT Block protection Figure 19. In-System Equipment Chip Unprotect flowchart START Set-up PROTECT ALL BLOCKS n=0 CURRENT BLOCK = 0 RP = VID WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Unprotect WRITE 60h ANY ADDRESS WITH A0 = VIL, A1 = VIH, A6 = VIH Wait 10ms Verify WRITE 40h ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH Wait 4µs READ DATA ADDRESS = CURRENT BLOCK ADDRESS A0 = VIL, A1 = VIH, A6 = VIH NO End NO ++n = 1000 YES DATA = 00h INCREMENT CURRENT BLOCK YES LAST BLOCK NO YES RP = VIH RP = VIH ISSUE READ/RESET COMMAND ISSUE READ/RESET COMMAND FAIL PASS AI03472 51/53 Revision history M29F800DT Revision history Table 28. Document revision history Date Revision 13-Dec-2001 -01 First Issue 21-Jan-2002 -02 VIH(max) value corrected -03 Description of Ready/Busy signal clarified (and Figure 13: Reset/Block Temporary Unprotect AC waveforms modified) Clarified allowable commands during block erase Clarified the mode the device returns to in the CFI Read Query command section 4.0 Revision numbering modified: a minor revision will be indicated by incrementing the digit after the dot, and a major revision, by incrementing the digit before the dot (revision version 03 equals 3.0). Erase Suspend Latency Time (typical) and Data Retention parameters added to Table 6: Program, Erase times and Program, Erase Endurance cycles, and notes added to the table. Figure 1: Logic diagram, and Figure 7: Data Toggle flowchart corrected. Lead-free package options E and F added to Table 18: Ordering information scheme. Document promoted to full datasheet. 4.1 TSOP48 package information updated (see Figure 15: TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package outline and Table 17: TSOP48 – 48 lead Plastic Thin Small Outline, 12 x 20mm, package mechanical data). Cross-references updated in Appendix B: Common Flash Interface (CFI) on page 42. Temperature range 3 added. 5 Changed document to new template; indicated that Ready/Busy Output now available for both SO44 and TSOP48 packages (see Table 1.: Signal names); removed temperature range 3 from Table 9 and Table 18; ecopack compliant 01-Mar-2002 17-Feb-2003 08-Jul-2003 24-Aug-2006 52/53 Revision details M29F800DT Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries (“ST”) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. 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